The main constraint appears to be the number of available GPIO's. For 8-bit projects the bus can take a large number of pins, not leaving a lot for the other functions.
Annoyingly the RP2040 has 30 GPIOs but the official Pico boards only break 26 of them out, which seems like an unforced error given the layout would have enough pins for all of them if it had less than 8 redundant GND pins. Those spare GPIOs are used to connect the WiFi coprocessor on the Pico W, but on the regular Pico one of them is just used for the onboard LED and the other 3 aren't connected to anything.
The redundant GND pins are necessary for signal integrity and low EMI when running at higher speeds; the high speed signals need a return current path with as little loop area as possible, so you want those signal pins close to GND on the connector.
On the RP2040 this is solved by having a huge ground pad in the middle[1], as it has somewhat modest needs.
On modern CPUs there are tons of "redundant" ground pins sprinkled all over[2]. Just about every high-speed GPIO pin and power pin has it's own ground pin right next to it.
Keep in mind "high speed" mostly relates to having fast edges. You can have EMI issues with a "slow" 1MHz signal if the edges have rise/fall times are say a few ns, which modern microcontrollers can do.
